Because a clock speed is limited by semiconductor process, and a wider bandwidth and lower power consumption are required in an analog-to-digital converter (ADC), the ADC is preferred to have a lower oversampling ratio (OSR). In addition, in some ADC designs, a multi-level digital-to-analog converter (DAC) is implemented to reduce a quantization noise, however, using the multi-level DAC may induce an element mismatch issue. To improve element mismatch issue, a dynamic element matching (DEM) circuit is positioned before the DAC to shape DAC mismatch to reduce the mismatch error. However, the DEM circuit becomes ineffective when low OSR is applied.